sample_pass Project Status (05/18/2013 - 13:53:31)
Project File: fmc150_ISE_14_4.xise Parser Errors: No Errors
Module Name: sample_pass Implementation State: Programming File Not Generated
Target Device: xc6vlx240t-1ff1156
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSat May 18 13:53:26 2013
WebTalk Log FileCurrentSat May 18 13:53:31 2013

Date Generated: 05/18/2013 - 13:53:31